1. Field of the Invention
The present invention relates to a reference voltage generation circuit that outputs a reference voltage which does not depend on temperature.
2. Description of the Related Art
A reference voltage generation circuit called a bandgap circuit is generally in wide use for providing a reference voltage dependent neither on temperature nor on a power-supply voltage. For example, the bandgap circuit adds a voltage of a forward-biased pn junction and a PTAT (Proportional To Absolute Temperature) voltage that is proportional to absolute temperature (T). It is known that the voltage of the forward-biased pn junction, if approximated by a linear expression, exhibits negative linear dependency on absolute temperature (hereinafter, also referred to as CTAT (Complementary To Absolute Temperature). Therefore, adding the voltage of the forward-biased pn junction and a proper PTAT voltage results in the reference voltage not dependent on temperature. As a bandgap circuit of this type, various kinds of circuits have been devised and put into practical use (for example, see FIG. 5 in M. C. Weng et al., “Low Cost CMOS On-Chip and Remote Temperature Sensors”, IEICE Transactions on Electronics, Vol. E84-C, No. 4, pp. 451-459, April 2001, and FIG. 1 of U.S. Pat. No. 6,462,612 B1).
FIG. 1 shows an example of a typical bandgap circuit. The bandgap circuit in FIG. 1 includes pnp bipolar transistors Q1, Q2 (hereinafter, the bipolar transistors are also referred to as BJT), resistors R1a, R2a, R3a (resistance values thereof are also denoted by R1a, R2a, R3a), and an operational amplifier AMP1a. GND is a GND voltage, BGROUT is an output reference voltage, and NODE1, IMa, and IPa are internal nodes. Values accompanying the resistors are examples of the resistance values. Numerals (×1, ×10) accompanying the BJTQ1, Q2 represent an example of a relative area ratio of the BJT Q1, Q2.
A base-emitter voltage of a transistor or a forward voltage Vbe of a pn junction is given by the expression (1).Vbe=Veg−a·T  (1)
Here, Veg is a bandgap voltage of silicon, T is absolute temperature, a is a temperature coefficient of the forward voltage Vbe. A value of a depends on a bias current of the pn junction. However, in a practical field, the value of a is known to be about 2 mV/° C. Further, the bandgap voltage Veg is about 1.2 V.
The relation of an emitter current IE of a BJT and the forward voltage Vbe is given by the expression (2). Here, IS is a constant proportional to an emitter area of a transistor, q is a charge of an electron, and k is a Boltzmann constant.IE=IS·exp {q·Vbe/(k·T)}  (2)
When a voltage gain of the operational amplifier AMP1a is sufficiently large, voltages of the inputs IMa and IPa of the operational amplifier AMP1a are equal owing to negative feedback by the operational amplifier AMP1a. If a ratio of the resistance values of the resistors R1a, R2a is, for example, 1:10 (100k:1M) as shown in FIG. 1, a ratio of magnitudes of currents flowing to the BJTQ1, Q2 is 10:1. If the current flowing through the BJTQ2 is I, the current flowing through the BJTQ1 is I×10. I×10 and I written under the BJTQ1, Q2 in FIG. 1 represent the relative relation between the currents flowing through the BJTQ1, Q2. If an emitter area ratio of the BJTQ1, Q2 is 1:10, a ratio of IS for the BJTQ1, Q2 in the expression (2) is 1:10. ×1, ×10 accompanying the BJTQ1, Q2 represent the relative relation of the emitter areas thereof.
Emitter currents of the BJTQ1, Q2 are given by the expressions (3), (4) respectively based on the expression (2), where Vbe1 is a base-emitter voltage of the BJTQ1 and Vbe2 is a base-emitter voltage of the BJTQ2. Performing the division of the both sides of the expressions (3), (4) gives the expression (5).I×10=IS·exp {q·Vbe1/(k·T)}  (3)I=IS×10·exp {q·Vbe2/(k·T)}  (4)100=exp {q·Vbe1/(k·T)−q·Vbe2/(k·T)}  (5)
A difference ΔVbe (ΔVbe=Vbe1−Vbe2) between the base-emitter voltages of the BJTQ1, Q2 is given by the expression (6).ΔVbe=(k·T/q)·ln(100)  (6)
The difference ΔVbe between the base-emitter voltages of the BJTQ1, Q2 is expressed by the expression (6), by using “ln(100)” and “(k·T/q)”, “ln(100)” being a logarithm of a ratio of current densities of the BJTQ1, Q2, and “(k·T/q)” being a thermal voltage. This voltage ΔVbe is equal to a voltage across both ends of the resistor R3a, so that a current of ΔVbe/R3a flows through the resistors R2a, R3a. Therefore, a voltage VR2a across both ends of the resistor R2a is given by the expression (7).VR2a=ΔVbe·R2a/R3a  (7)
A voltage of the node IMa is equal to the forward voltage Vbe1 being a voltage of the node IPa, and therefore, an output reference voltage BGROUT is given by the expression (8).BGROUT=Vbe1+ΔVbe·R2a/R3a  (8)
The forward voltage Vbe1 of the pn junction decreases as temperature rises, that is, it has negative temperature dependency (see the expression (1)). On the other hand, the difference ΔVbe between the base-emitter voltages of the BJTQ1, Q2 increases in proportion to temperature (see the expression (6)). Therefore, if a constant is properly selected, the output reference voltage BGROUT has a value not dependent on temperature. The output reference voltage BGROUT at this time is about 1.2 V corresponding to the bandgap voltage of silicon.
The bandgap circuit shown in FIG. 1 is advantageous in that the reference voltage can be generated with a relatively simple circuit. However, in an actual integrated circuit, due to element variance, input voltages of an operational amplifier are not completely the same (this voltage difference between the inputs is called an offset voltage). The offset voltage depends on each operational amplifier. However, a typical offset voltage is known to be about +10 mV˜about −10 mV. Therefore, the output reference voltage BGROUT is influenced by the offset voltage of the operational amplifier (AMP1a in FIG. 1) included in the bandgap circuit. That is, depending on the offset voltage of the operational amplifier included in the bandgap circuit, achieved accuracy of the output reference voltage BGROUT becomes low.
FIG. 2 shows an influence of the offset voltage of the operational amplifier in the circuit shown in FIG. 1. The same reference symbols are used to designate the same elements as the elements described in FIG. 1, and detailed description thereof will be omitted. A bandgap circuit in FIG. 2 includes an ideal operational amplifier IAMP1 in place of the operational amplifier AMP1a in FIG. 1. Further, an offset voltage VOFF (a value of the offset voltage VOFF is also denoted by VOFF) corresponding to the offset voltage of the operational amplifier AMP1a is added to one input side of the ideal operational amplifier IAMP1. IIM in FIG. 2 is an input terminal on the one side of the ideal operational amplifier IAMP1.
If the offset voltage of the ideal operational amplifier IAMP1 is 0 mV, the offset voltage VOFF of the operational amplifier influences the output reference voltage BGROUT in the following manner. In the ideal circuit in FIG. 1, the voltages of the node IMa and the node IPa are equal. On the other hand, in an actual circuit, voltages of the input IIM and a node IPa of the ideal operational amplifier IAMP1 are equal. Therefore, a voltage of a node IMa is the sum of the voltage of the node IPa and the offset voltage VOFF. The voltage of the node IMa, which is denoted by VIMa, is given by the expression (9).VIMa=Vbe1+VOFF  (9)
From the expression (9), a voltage VR3a applied to a resistor R3a in FIG. 2 is given by the expression (10).VR3a=ΔVbe+VOFF  (10)
From the expression (10), a voltage VR2a across both ends of a resistor R2a is given by the expression (11).VR2a=(ΔVbe+VOFF)·R2a/R3a  (11)
From the expression (11), the output reference voltage BGROUT is given by the expression (12).BGROUT=Vbe1+VOFF+(ΔVbe+VOFF)·R2a/R3a  (12)
In the example in FIG. 2, a resistance ratio R2a/R3a is “5”, and therefore, the output reference voltage BGROUT is the sum of an ideal value and the offset voltage multiplied by six.
In order to reduce the influence of the offset voltage VOFF, in the examples in FIG. 1 and FIG. 2, the area of the BJTQ2 is made ten times as large as the area of the BJTQ1, and the current flowing through the BJTQ1 is made ten times as large as the current flowing through the BJTQ2. Consequently, the difference ΔVbe between the base-emitter voltages of the BJTQ1, Q2 is about 120 mV, for example, when T=300K (see the expression (6)). Thus, the difference ΔVbe between the base-emitter voltages of the BJTQ1, Q2 has a large value relative to the offset voltage VOFF. However, also in this case, the offset voltage VOFF influences the output reference voltage BGROUT. For example, with T=300K, Vbe1=600 mV, and R2a/R3a=5, the output reference voltage BGROUT is about 1200 mV (see the expression (6) and the expression (8)). At this time, a voltage six times (1+R2a/R3a) as high as the offset voltage VOFF is added in the output reference voltage BGROUT (see the expression (12)). The value of the output reference voltage BGROUT shown in FIG. 2 indicates the influence of this offset voltage.
To eliminate the influence of the offset voltage VOFF, there has been proposed a bandgap circuit (Chopper-stabilized BGR) adopting a chopper circuit (for example, FIG. 2 of U.S. Pat. No. 6,462,612B1, Japanese Unexamined Patent Application Publication No. Hei 11-143564, FIG. 6 in M. C. Weng et al., “Low Cost CMOS On-Chip and Remote Temperature Sensors”, IEICE Transactions on Electronics, Vol. E84-C, No. 4, pp. 451-459, April 2001, FIG. 3 in Y. S. Shyu et al., “A 0.99 μA Operating Current Li-ion Battery Protection IC”, IEICE Transactions on Electronics, Vol. E85-C, No. 5, pp. 1211-1215, May 2002, FIG. 4 in F. Fruett et al., “Minimization of the Mechanical-Stress-lnduced Inaccuracy in Bandgap Voltage References”, IEEE Journal of Solid-State Circuits, Vol. 38, No. 7, pp. 1288-1291, July 2003, and FIG. 3 in A. Bakker et al., “Micropower CMOS Temperature Sensor with Digital Output, “IEEE journal of Solid-State Circuits, Vol. 31, No. 7, pp. 933-937, July 1996).
FIG. 3(a) and FIG. 3(b) show an operational principle of a conventional chopper-stabilized bandgap circuit. The same reference symbols are used to designate the same elements as the elements described in FIG. 2, and detailed description thereof will be omitted. A bandgap circuit in FIG. 3(a) is structured such that switches SW1a, SW2a, SW3a, SW4a and a low-pass filter LPF are added to the bandgap circuit in FIG. 2. An ideal operational amplifier IAMP2 is an ideal operational amplifier circuit, a reference voltage BGROUT is an output reference voltage, an output REFOUT is an output of the low-pass filter LPF, VOFF is an offset voltage, and NODE1, IMa, IPa, NODE2, and NODE3 are internal nodes. Signal names φ1, φ2 accompanying the switches SW1a-SW4a indicate periods during which the respective switches are on. The switches SW2a, SW3a are on during periods in which φ1 is H (High level) (hereinafter also referred to as φ1 periods), and the switches SW1a, SW4a are on during periods in which φ2 is H (hereinafter, also referred to as φ2 periods). FIG. 3(b) shows the relation between the timings of the signals φ1, φ2 and the output reference voltage BGROUT.
The bandgap circuit in FIG. 3(a) operates similarly to the bandgap circuit in FIG. 2 during the periods in which φ1 is H (φ1 period). As described in FIG. 2, for example, the sum of the ideal bandgap output and the offset voltage VOFF multiplied by 6 is outputted as the output reference voltage BGROUT. The output reference voltage BGROUT at this time is, for example, ideal value IDL (1200 mV)+6×VOFF. In the bandgap circuit in FIG. 3(a), by the switches SW1a-SW4a, the connection of nodes IMa, IPa to the nodes NODE2 and NODE3 is interchanged. That is, in the φ1 periods, the node IMa is connected to the node NODE2 and the node IPa is connected to the node NODE3, and in the φ2 periods, the node IMa is connected to the node NODE3 and the node IPa is connected to the node NODE2. Further, the ideal operational amplifier IAMP2 operates in such a manner that an input from a − input terminal of the ideal operational amplifier IAMP2 is defined as a − input in the φ1 periods and as a + input in the φ2 periods. Similarly, the ideal operational amplifier IAMP2 operates in such a manner that a + input of the ideal operational amplifier IAMP2 is defined as a + input in the φ1 periods and as a − input in the φ2 periods. Consequently, negative feedback by the ideal operational amplifier IAMP2 is realized also in the φ2 periods. Therefore, the output reference voltage BGROUT has a value of ideal value IDL (1200 mV)−6×VOFF in the φ2 periods. Consequently, the output reference voltage BGROUT in the φ1 periods has a value of ideal value IDL(1200 mV)+6×VOFF, and that in the φ2 periods has a value of ideal value IDL(1200 mV)−6×VOFF (FIG. 3(b)).
Further, the output reference voltage BGROUT that changes in synchronization with the signals φ1, φ2 is inputted to the low-pass filter LPF. The output REFOUT of the low-pass filter LPF becomes a reference voltage not including an error ascribable to the offset voltage VOFF. Specifically, in the bandgap circuit in FIG. 3(a), the error ascribable to the offset is converted into an AC component by using the signals φ1, φ2, and an error component is removed by the low-pass filter LPF. Consequently, the chopper-stabilized bandgap circuit outputs an ideal reference voltage.
FIG. 4 shows an example of a concrete circuit configuration of the chopper-stabilized bandgap circuit. The same reference symbols are used to designate the same elements as the elements described in FIG. 3(a) and FIG. 3(b), and detailed description thereof will be omitted. In the bandgap circuit in FIG. 4, an operational amplifier circuit operating as a chopper amplifier includes nMOS transistors NM1a, NM2a, NM3a, pMOS transistors PM1a, PM2a, PM3a, PM4a, and switches SW1a-SW8a. In FIG. 4, VDD is a power-supply voltage, a bias voltage PBIAS1a is a bias voltage, and nodes NODE1, IMa, IPa, NODE2, NODE3, ND1, ND2, NG1, NG2 are internal nodes. Signal names φ1, φ2 accompanying the switches SW1a-SW8a indicate periods during which the respective switches are on. The switches SW2a, SW3a, SW5a, SW7a are on during periods in which φ1 is H, and the switches SW1a, SW4a, SW6a, SW8a are on during periods in which φ2 is H.
By the switches SW1a-SW4a, one of gates of the transistors PM2a and PM3a is connected to the node IMa and the other gate is connected to the node IPa. For example, in the φ1 periods, the gate of the transistor PM2a is connected to the node IMa and the gate of the transistor PM3a is connected to the node IPa. Further, since the switch SW5a is on, the transistor NM1a becomes a load of diode-connection. Further, since the switch SW7a is on, a gate of the transistor NM3a is connected to the node ND2. In the φ2 periods, the gate of the transistor PM3a is connected to the node IMa. Further, since the switches SW6a, SW8a are on, the transistor NM2a becomes a load of diode-connection, and the gate of the transistor NM3a is connected to the node ND1. Therefore, both in the φ1 periods and the φ2 periods, negative-feedback loop is formed. The + input and the − input of the operational amplifier including the transistors PM2a, PM3a and the transistors NM1a, NM2a are interchanged in the φ1 periods and the φ2 periods. Consequently, offset voltages of the operational amplifier in the φ1 periods and the φ2 periods have values substantially equal to each other with opposite signs. Therefore, on average, the offset voltage does not occur.
The bandgap circuit adopting the chopper circuit shown in FIG. 3(a) and FIG. 4 reduces an error of the output reference voltage BGROUT ascribable to the offset voltage of the operational amplifier.
In FIG. 4, the configuration example in which the chopper circuit is adopted as a standard 2-stage amplifier is shown. Besides, also known is a bandgap circuit adopting a chopper circuit as a folded cascode circuit (for example, FIG. 4 in F. Fruett et al., “Minimization of the Mechanical-Stress-Induced Inaccuracy in Bandgap Voltage References, “IEEE journal of Solid-State Circuits, Vol. 38, No. 7, pp. 1288-1291, July 2003, and FIG. 11 in A. Bakker et al., “A CMOS Nested-Chopper Instrumentation Amplifier with 100-nV Offset”, IEEE Journal of Solid-State Circuits, Vol. 35, No. 12, pp. 1877-1883, December 2000).
FIG. 5(a) to FIG. 5(c) show an example of a circuit adopting a chopper circuit as a folded cascode circuit. The folded cascode circuit in FIG. 5(a) includes nMOS transistors NM4a, NM5a, NM6a, NM7a, pMOS transistors PM5a, PM6a, PM7a, PM8a, PM9a, PM10a, PM11a, and chopper part circuits CHS1, CHS2, CHS3. In FIG. 5(a), VDD is a power-supply voltage, GND is a GND voltage, input nodes IN1, IN2 are input terminals of the amplifier, an output node OUT is an output terminal of the amplifier, nodes ND3, ND4, PG1 are internal nodes, bias voltages PBIAS2a, PBIAS3a are bias voltages of the pMOS transistors, bias voltages NBIAS1a, NBIAS2a are bias voltages of the nMOS transistors. FIG. 5(b) shows a configuration of the chopper part circuits CHS1-CHS3. Each of the chopper part circuits CHS1-CHS3 includes switches SWC1, SWC2, SWC3, SWC4. Signals φ1, φ2 accompanying the switches SWC1-SWC4 indicate periods during which the respective switches are on. Each of the switches is on during periods in which the corresponding signal is H and is off during periods in which the corresponding signal is L (Low level). FIG. 5(c) shows an example of timings of the signals φ1, φ2.
The chopper part circuits CHS1-CHS3 are circuits that select whether two signals are to be transmitted straight or in an intersecting manner (by interchanging the signals). That is, in periods in which the signals are transmitted straight (the periods in which the signal φ1 is H), a node NODEC1 and a node NODEC3 are connected, and a node NODEC2 and a node NODEC4 are connected. In periods in which the signals are transmitted in the intersecting manner (the periods in which the signal φ2 is H), the node NODEC1 and the node NODEC4 are connected and the node NODEC2 and the node NODEC3 are connected. The chopper part circuits CHS1-CHS3 interchange the relation of all the signals in the periods in which the signals are transmitted straight and in the periods in which the signals are transmitted in the intersecting manner. Therefore, the folded cascode circuit in FIG. 5(a) operates with the same polarity in the periods in which the signals are transmitted straight and in the periods in which the signals are transmitted in the intersecting manner.
In the above, a description is made on a design of the conventional circuit contrived to reduce the influence that the offset voltage of the operational amplifier gives to the output voltage of the bandgap circuit. But the output voltage of the bandgap circuit is influenced not only by the offset voltage of the operational amplifier but also by an error in resistors or in the base-emitter voltages Vbe of pnp bipolar transistors. In order to reduce the error in the resistors or in the base-emitter voltages Vbe of the pnp bipolar transistors, trimming has been generally performed (for example, FIG. 2 in Japanese Unexamined Patent Application Publication No. 2001-217393, FIG. 3 in Japanese Unexamined Patent Application Publication No. Hei 10-260746, FIG. 5 in National Publication No. Hei 10-508401, FIG. 1 in Japanese Unexamined Patent Application Publication No. Hei 9-260589, FIG. 1 in Japanese Unexamined Patent Application Publication No. 2004-341877, FIG. 9 of U.S. Pat. No. 6,590,372B1, and FIG. 4 of U.S. Pat. No. 6,812,684B1). For example, as a method of resistor trimming, there has been known a method of adjusting the total resistance value by parallel-connecting sets of a resistor and a fuse connected in series and cutting the fuses by a laser or the like (for example, FIG. 6 in G. C. M. Meijer et al., “Temperature Sensors and Voltage References Implemented in CMOS Technology”, IEEE Sensors Journal, Vol, 1, No. 3, pp. 225-234, October 2001). Further, as a method called Zener zapping, there has been known a method in which sets of a resistor and a Zener device connected in parallel are connected in series and the Zener devices are broken in order to lower the resistance of the Zener devices, thereby adjusting the total resistance value.
FIG. 6 shows an example of a bandgap circuit adopting a circuit for trimming the area of transistors. The same reference symbols are used to designate the same elements as the elements described in FIG. 1, and detailed description thereof will be omitted. The bandgap circuit in FIG. 6 is structured such that the resistor R1a and the operational amplifier AMP1a are removed from the bandgap circuit in FIG. 1 and an operational amplifier AMP2a, pMOS transistors PM12a, PM13a, transistors Q2a, Q2b, Q2c, and switches SW10a, SW11a, SW12a are added thereto.
In order to generate a bandgap voltage, a PTAT voltage generated based on a difference ΔVbe between base-emitter voltages of BJTQ1, Q2 is added to a base-emitter voltage Vbe1 of the BJTQ1, as described by the expression (8). However, in an actual integrated circuit, a value of the base-emitter voltage Vbe itself of a transistor varies due to fluctuation in manufacturing conditions. The difference ΔVbe between Vbe of pnp bipolar transistors also varies due to fluctuation in manufacturing conditions. However, this variance is smaller than the variance in the absolute value of the base-emitter voltage Vbe of a transistor. Due to these variances, the bandgap voltage expressed by the expression (8) deviates from a design value. In order to reduce an error of the output voltage of the bandgap circuit due to these variances, the total area of the BJTQ2, Q2a, Q2b, Q2c is adjusted. For example, after the manufacturing, in order to adjust the PTAT voltage, the total area of the BJTQ2a, Q2b, Q2c that are connected in parallel to the BJTQ2 is adjusted by the switches SW10a-SW12a. Consequently, it is possible to adjust the output voltage of the bandgap circuit.
Further, in a bandgap circuit using MOS transistors, a value of an output voltage is also influenced by matching of the MOS transistors. As a method of improving the matching of the MOS transistors, dynamic element matching has been known (for example, FIG. 9 in G. C. M. Meijer et al., “Temperature Sensors and Voltage References Implemented in CMOS Technology”, IEEE Sensors journal, Vol. 1, No. 3, pp. 225-234, October 2001, FIG. 2 in RJ. Van De Plassche, “Dynamic Element Matching for High-Accuracy Monolithic D/A Converters”, IEEE Journal of Solid-State Circuits, Vol. SC-11, No. 6, pp. 795-800, December 1976, and V. G. Ceekala et al., “A Method for Reducing the Effects of Random Mismatches in CMOS Bandgap References”, ISSCC Digest of Technical Papers, pp. 23. 7, Feb. 2002).
FIG. 7(a) and FIG. 7(b) show an operational principle of a dynamic element matching circuit. The circuit in FIG. 7(a) includes PMOS transistors PM14a, PM15a, PM16a and switches SW13a-SW21a. VDD is a power-supply voltage, a bias voltage PBIAS4a is a bias voltage supplied commonly to gates of the transistors PM14a-PM16a, nodes NODE4-NODE9 are node names given for description, currents I1, I2, I3 are currents flowing through the nodes NODE7, NODE8, NODE9 respectively. Signals φ1a, φ2a, φ3a accompanying the switches SW13a-SW21a indicate periods in which the respective switches are on. The switches SW13a-SW2a are on during periods in which the respective signals φ1a, φ2a, φ3a are H, and are off during periods in which the respective signals φ1a, φ2a, φ3a are L. FIG. 7(b) shows the relation between the signals φ1a, φ2a, φ3a and the currents I1, I2, I3.
The principle of the dynamic element matching will be described by using FIG. 7(a) and FIG. 7(b). Ideally, currents of the transistors PM14a, PM15a, PM16a are equal when the transistors PM14a, PM15a, PM16a are made equal in a ratio W/L of a gate width W and a gate length L. However, in an actual integrated circuit, due to manufacturing variance, a threshold voltage Vth differs depending on each element. Therefore, even if MOS transistors are designed so as to be equal in the ratio W/L of the gate width W and the gate length L, current values thereof are not equal to one another. The dynamic element matching makes the values of the three currents I1, I2, I3 equivalently equal to one another by switching the transistors PM14a, PM15a, PM16a at equal time intervals. This signifies that, by time-averaging the currents, average currents of different values of currents can be equated”.
A description will be given on assumption that, for example, a current value of the transistor PM14a is 1.10, a current value of the transistor PM15a is 1.05, and a current value of the transistor PM16a is 0.85. When the signal φ1 is H, a value of the current I1 is the current value of the transistor PM14a, a value of the current I2 is the current value of the transistor PM15a, and a value of the current I3 is the current value of the transistor PM16a. When the signal φ2 is H, the value of the current I1 is the current value of the transistor PM15a, the value of the current I2 is the current value of the transistor PM16a, and the value of the current I3 is the current value of the transistor PM14a. When the signal φ3 is H, the value of the current I1 is the current value of the transistor PM16a, the value of the current I2 is the current value of the transistor PM14a, and the value of the current I3 is the current value of the transistor PM15a. Consequently, the current I1 exhibits a current waveform such that the current value thereof changes at equal time intervals in order of 1.10 (the current of the transistor PM14a), 1.05 (the current of the transistor PM15a), and 0.85 (the current of the transistor PM16a). Therefore, the average current of the current I1 comes to have an average value of the currents of the transistors PM14a, PM15a, PM16a. Likewise, the average current of each of the currents I2, I3 also comes to have the average value of the currents of the transistors PM14a, PM15a, PM16a. In this manner, even current sources (the transistors PM14a, PM15a, PM16a) whose current values are not completely the same are used, the averages of currents (the currents I1, I2, I3) flowing through branches thereof can be made equal to one another.
FIG. 8 shows another example of a typical bandgap circuit. In FIG. 1, the most standard circuit configuration is shown, but various configurations have been proposed as a configuration realizing the bandgap circuit (for example, U.S. Pat. No. 6,563,371B2, U.S. Pat. No. 6,489,835B1, U.S. Pat. No. 6,853,164B1, U.S. Pat. No. 6,366,071B1, U.S. Pat. No. 6,181,121B1, U.S. Pat. No. 6,147,548, U.S. Pat. No. 5,325,045, Japanese Patent Publication No. 3420536, and Japanese Unexamined Patent Application Publication No. Hei 11-134048). The circuit in FIG. 8 is one example among them. The same reference symbols are used to designate the same elements as the elements described in FIG. 6, and detailed description thereof will be omitted.
The bandgap circuit in FIG. 8 is structured such that the resistor R2a, the switches SW10a-SW12a, and the pnp transistors Q2a, Q2b, Q2c are removed from the bandgap circuit in FIG. 6 and operational amplifiers AMP3a, AMP4a, resistors R4a, R5a (resistance values thereof are also denoted by R4a, R5a), and pMOS transistors PM17a-PM20a are added thereto. Nodes AMPOUT1a, AMPOUT2a, AMPOUT3a, NODE10, and NODE11 are internal nodes. A size (area) ratio of BJTQ1, Q2 in FIG. 8 is, for example, 1:10.
The operation of the circuit in FIG. 8 will be described on assumption that the transistors PM12a, PM13a, and PM17a are equal in a ratio W/L of a gate width Wand a gate length L and currents with the same value flow therethrough. Owing to negative feedback by an operational amplifier AMP2a, a voltage of the node AMPOUT1a is determined to a voltage that causes voltages of a node IMa and a node IPa to be equal to each other. Since the currents with the same value flow through the transistors PM12a and PM13a, a voltage across both ends of a resistor R3a is given by the expression (13).ΔVbe=(k·T/q)·ln(10)  (13)
That is, currents proportional to absolute temperature (PTAT currents) flow through the transistors PM12a, PM13a. Since a current of the transistor PM17a is also equal to the currents of the transistors PM12a, PM13a, a PTAT current flows also through the transistor PM17a. 
Owing to negative feedback by the operational amplifier AMP3a, a voltage of the node AMPOUT2a is determined to a voltage that causes voltages of the node IPa and the node NODE10 to be equal to each other. Since the voltage of the node IPa is a base-emitter voltage Vbe1 of the BJTQ1, a voltage applied to the resistor R4a is also equal to the voltage Vbe1. Therefore, a current flowing through the transistor PM18a and the resistor R4a is Vbe1/R4a. Since the voltage Vbe1 has negative linear dependency on absolute temperature (CTAT: Complementary To Absolute Temperature), the current flowing through the transistor PM18a and the resistor R4a is also a CTAT current.
Here, it is assumed that the transistors PM18a, PM19a are equal in size, and currents equal to each other flow through the transistors PM18a, PM19a. The PTAT current flows through the transistor PM17a, while the CTAT current flows through the transistor PM19a. Consequently, a current equal to the sum of the PTAT current and the CTAT current flows to the resistor R5a. At a properly set ratio of the PTAT current and the CTAT current, the current resulting from the addition of the PTAT current and the CTAT current is not dependent on temperature. This current not dependent on temperature is converted to a voltage by the resistor R5a. Consequently, an output reference voltage BGROUT not dependent on temperature can be obtained.
Further, it is generally known that even with the same gate-source voltage, if drain voltages are different, drain currents do not have the same value due to, for example, a channel length modulation effect. The operational amplifier AMP4a and the transistor PM20a are intended for solving this current mismatch. Owing to a negative-feedback operation of the operational amplifier AMP4a, voltages of the node NODE11 and the node IPa are equal to each other. Accordingly, drain voltages of the transistors PM17a, PM12a, and PM13a are equal to one another. Likewise, drain voltages of the transistors PM18a, PM19a are also equal to the voltage of the node IPa. Therefore, the current mismatch among the transistors PM17a, PM12a, and PM13a and the current mismatch between the transistors PM18a and PM19a are solved.
As has been described hitherto, the circuit configuration of the bandgap circuit, namely, the reference voltage generation circuit, and the method for realizing the same are wide ranging.
The reference voltage generation circuit adopting the conventional chopper circuit or dynamic element matching circuit reduces the influence that the offset voltage of the operational amplifier and matching of the MOS transistors give to the output reference voltage. However, there is a problem that an error in the output reference voltage ascribable to variance in the resistors and the base-emitter voltages Vbe of the bipolar transistors is not solved. Moreover, the reference voltage generation circuit adopting the conventional trimming circuit can correct the error in the output reference voltage ascribable to variance in the resistors or the base-emitter voltages Vbe of the bipolar transistors. For example, it is possible to correct the output reference voltage by adjusting ΔVbe·R2a/R3a (PTAT voltage) in the expression (8) and the forward voltage Vbe1 of the pn junction or the CTAT voltage to desired values. However, with the conventional circuit configuration, it is not possible to independently measure the PTAT voltage or the CTAT voltage. In a case where the adjustment is thus made based on one output reference voltage resulting from the addition of two voltages, namely, the PTAT voltage and the CTAT voltage, measurement and adjustment are repeated under many temperatures until the values approximates expected values. Therefore, accurate correction of the output reference voltage in a short test time (namely, at low cost) is difficult. Further, the conventional resistor trimming circuit or the like has a special Zener diode, and it is necessary to apply a high voltage to break the Zener diode. Therefore, the conventional resistor trimming circuit cannot be applied in typical and low-cost CMOS processes.